Embedded Wafer Level Packaging (eWLP) and Embedded wafer Ball Grade array (eWLB) (also known as “Fan out” processes) are built by the following process:    i. Dicing (sawing) a silicon wafer to individual silicon dice;    ii. Placing each silicon die “face down” (or “Flip Chip”) by a pick and place device onto a mold (such as a tape). The tape forms a mold in which a casting will be molded.    iii. Molding a casting material that (optionally—after curing) provides a frame around each silicon die to provide molded dies that form a reconstructed wafer (also known as fan out wafer or a molded wafer), wherein each molded die has a larger area for placing interconnects—that area includes the surface of the silicon die and the frame that surrounds the silicon die;    iv. Applying (patterning) of a redistribution layer (RDL) that includes multiple conductors that are expected to electrically connect pads of the silicon die and interconnects (such as solder bumps) that should be formed on the entire surface of the molded die;    v. Performing a bumping process to complete the manufacturing process and provide interconnects that can be connected to printed circuit boards or to any other element.
Various errors may include: silicon die misalignment (along any axis, including rotation, in relation to the entire wafer, to another die to an expected position), height differences between the silicon die and the frame, misalignments between the silicon die and the frame, conductor misalignment and interconnects misalignment.
Such fan out wafers may exhibit an uncertainty of location, shift and tilt of each individual die thus complicating (and introducing errors) in the manufacturing process—usually patterning of RDL, applying bumps, TSV and the like). This may cause process yield loss or final product quality and reliability issues of the end product during its service.
This yield loss or device quality and reliability may result from major alignment problems related to the interface between the silicon die and the frame and the rest of the dies on the fan-out wafer:    (a) Translation and rotation errors caused during pick, flip and place of each individual silicon die—leading to horizontal (X,Y) misplacement and rotation (Theta) issues between pads on each silicon die (as it located de-facto) and the orientation of the image of RDL, which should be applied on each silicon die and the frame during patterning and other manufacturing processes; and    (b) Surface height difference between the silicon die and the frame, which may lead to the pattern distortion during the RDL patterning process and manufacturing problems during RDL and further steps manufacturing.
Each manufacturing stage assumes that all dice on fan-out wafer are perfectly aligned within single, constant and predictable die index (delta-X and delta-Y) and have zero rotation and Z tilt/roll.
This fault free assumption can result from using manufacturing equipment (especially for patterning, probing, testing and bumping) that were designed for the manufacturing of full, non-diced, wafers. Failing to recognize or adjust the variations of location and other attributes of each individual die results in unrecoverable yield loss.